The Micro Architecture Level.ppt

WebDB05 The Micro Architecture Level Mic-1 architecture on Tanenbaum’s book Dept. of Computer Science Virginia Commonwealth University Mic-1 block diagram 1. Why the C bus is represented as a bit map? while B bus register is encoded in a 4 bit field 2. Give a circuit diagram for “High bit”. Simple answer? F =(JAMZ AND Z) OR (JAMN AND N) OR NEXT_ADDRESS[8] Calculation of Next Address Calculation of Next address Calculation of Next Address 3. Next address = 0x1FF and use JMPC? 4. What if add k=5 after IF? 5 IJVM translation of i= k + n + 5 6. Give the JAVA statement 7. Is it possible? 8.Why not: if_cmpeq3 Z = TOS-MDR;rd 9. How long it will takes? Microinstruction Microinstruction Microinstruction: load k Microinstruction: iadd Microinstruction: istore Microinstruction: Homework 10 speed with Mic-2 Mic-2 How to design IFU? 11 Write microcode for POPTWO 12 loading locals 0- through 4 13 ISHR (Arithmetic Shit Right) 14 ISHL 15 INVOKRVIRTUAL 16 DLOAD in Mic-2 17 finite state machine 18 equivalents? 19 finite state machine 20 IFU with a 5 byte shifter register 21 larger shifter for IFU 22 Mic 2 : go to 23 speed with Mic-2 24 Mic-4 25 two level cache 26 3 way cache? 27 pipeline 28 prefetch 29 cycle 6 30 dependency in pipeline 31 Rewrite Mic-1 intepreter 32 write simulator CMSC 312 Computer Organization Hongsik Choi Only one register can be loaded onto B bus, yet more than one register can be selected to be loaded from C bus JAMC MBR7 Addr7 MPC7 MBR0 Addr0 MPC0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Z JAMZ N JAMN Addr8 MPC8 MPC points to the next microinstruction. it is computed from Next_Address JAM fields the ALU status N and Z, the MBR If JMPC MPC[0:7] = Addr[0:7] Else Addr[0:7] OR MBR[0:7]. MPC[8] = Addr[8] or (JAMZ and Z) or (JAMN and Z) Does it make sense? What if Next address is 0xFF? 111111111 (Next Address) bbbbbbbb (MBR) No, Meaningless Next address is usually, 0x00 or 0x100 Why? K = 5 BIPUSH 5 ISTORE k ILOAD k ILOAD