EE 587SoC Design amp; Test.ppt

Scan Design Scan Design In test mode, all flip-flops functionally form one or more shift registers The inputs and outputs of these shift registers are made into PI/Pos Using the test mode, all flip-flops can be set to any desired states The states of the flip-flops are observed by shifting the contents of the scan register out Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. Scan Design Rules Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. Scan Flip-Flop (SFF) D TC SD CK Q Q MUX D flip-flop Master latch Slave latch CK TC Normal mode, D selected Scan mode, SD selected Master open Slave open t t Logic overhead Scannable Flip-flop Bed-of-Nails Tester Concept Need for Standard Bed-of-nails printed circuit board tester We put components on both sides of PCB replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips Boundary Scan Architecture Lecture 4 * Lecture 4 * * EE 587SoC Design Test Partha Pande School of EECS Washington State University pande@eecs.ws