Processor Types And Instruction Sets.ppt

Processor Types And Instruction Sets Barak Perelman CS147 Prof. Lee ISA Instruction Set Architecture All programmer accessible hardware instructions for that hardware System as Whole CPU (Central Processing unit) interaction with main memory (its internal memory) Input Output System Bus CPU connected with main memory I/O via System Bus CPU – generates addresses placed on Address bus Memory – receives addresses from Address bus THIS PROCESS NEVER REVERSED CPU Memory Since CPU executes instructions, and all instructions/data stored in Memory. Instructions/data must be loaded to CPU registers, and results stored back in Memory. A Bit about Memory (no pun intended) Memory is a collection of consecutive cells = 1 byte (8 bits) Each cell has address/memory location Group of cells = WORD usually 4 Bytes Convention: WORD accessed by referencing byte with lowest byte Computers memory is an “array” of bytes CPU – 2 Sections 1. Data Section – Registers ALU 2. Control Section – interprets instructions and controls register transfers – executes instructions stored in main memory Interface between Data and Control Units Register 1: Program Counter (PC) or IP (“Instruction Pointer” in IA) – address of instruction executed Register 2: Instruction register (IR) – fetched instruction (PC pointed) stored in IR and interpreted FETCH-EXECUTE CYCLE Fetch next instruc. To be exec. from memory Decode operation code Read operand(s) from main memory if any Exec. Instruc. and store results if any Go step 1 Control unit Data unit (datapath) again… Control unit – decodes instruction after fetch, and performs specific action. Coordinates this in execution of program. Datapath – Collection of registers (register file) , arithmetic and logic unit, and other registers. Datapath - Register file Register file – used like temporary “memory” during computation. Can be many register files (depend on CPU). Each has own address (in sequence, like main memory, but with much smaller addresses