Lecture 27Memory and Delay-Fault Built-In Self-Testing.ppt

Copyright 2001, Agrawal Bushnell VLSI Test: Lecture 27 Lecture 27Memory and Delay-Fault Built-In Self-Testing Definitions Static RAM March Test BIST SRAM BIST with a MISR Neighborhood Pattern Sensitive Fault (NPSF) DRAM BIST Transparent testing Complex examples Delay fault BIST Summary Definitions Concurrent BIST – Memory test that happens concurrently with normal system operation Transparent testing – Memory test that is non-concurrent, but preserves the original memory contents from before testing began LFSR and Inverse Pattern LFSR NOR gate forces LFSR into all-0 state Get all 2n patterns Up / Down LFSR Preferred memory BIST pattern generator Satisfies March test conditions Up / Down LFSR Pattern Sequences Mutual Comparator Test 4 or more memory arrays at same time: Apply same test commands addresses to all 4 arrays at same time Assess errors when one of the di (responses) disagrees with the others Mutual Comparator System Memory BIST with mutual comparator Benefit: Need not have good machine response stored or generated Parallel Memory BIST Parallel Memory March C Add MUX to inputs of write drivers: Selects normal data input or left neighbor sense amplifier output Creates shift register during self-test Generalize any March test to test n-bit words in array rows (x)n means repeat x operations n times Example: March Cn { (w0)n (r0, w0)n; (r0, w1)n (r1, w1)n; (r1, w0)n (r0, w0)n; (r0, w1)n (r1, w1)n; (r1, w0)n (r0, w0)n; (r0, w0)n (r0, w0)n} MATS+ RAM BIST For single-bit word – can generalize to n-bit words Need Address MUX – switch row decoder from normal input to address stepper (which is the Up/Down LFSR) # states needed: 2 x # March elements + 3 Three extra states: Start Error Correct Chip area overhead: 1 to 2 % -- widely used State Transition Diagram SRAM BIST with MISR Use MISR to compress memory outputs Control aliasing by repeating test: With different MISR feedback polynomial With RAM