採用次取樣及其共用技術之八位元管線式類比數位轉換器.pdfVIP

The 15th Conference on the Wireless across the Taiwan Straits A 8-Bit Pipelined ADC Using Sub-Sampling and Sharing Techniques Mingchieh Tsai , Shangwen Yu Electrical Engineering Tatung University, Zhongshan, 104, Taiwan Abstract: An analog to digital interface is required between the received analog signal and DSP system and portable consumer electronics. The demand for low-power integrated circuits is indispensable. Among ADC architectures, pipelined ADCs are the most suitable for medium/high speed and resolution applications. In this thesis, a 8-bit 50-MHz pipelined analog-to-digital converter consisting of 1.5-bit/stage has been designed in TSMC 0.18μm 1P6M CMOS process. In order to decrease noise interference, the whole circuit is designed by fully differential structure. And for achieving a low power and small area pipelined ADC, this thesis merges op-amp sharing, sub-sampling and sub-ADC sharing. The pipeline ADC is simulated by HSPICE. For 1.123046875MHz sine wave input, the SNDR is 47.66 dB, the differential input range is ± 1V, and the power consumption is 62.44mW. Keywords: Pipelined ADC ;Sub-sampling ;Opamp sharing ;Sub-ADC sharing. 採用次取樣及共用技術之八位元管線式類比數位轉換器 蔡明傑*a、游尚文 b 私立大同大學電機工程學系 中山區 台灣 104 mctsai@ttu.edu.tw a 摘 要: 本文著重於低消耗功率及 小的 局面 ，因此 合 算放大器共用、次取 技 及子 比 較 佈 積 結 運 樣 術 類 數 位 器共用，使 局面 和消耗功率有效的 ，且 了降低 干 ，整 路 用全差 架 。本 轉換 佈 積 縮減 為 雜訊 擾 體電 採 動 構 文 程 是 用台 0.18μm 1P6M 互 式金氧半 程，在取 率 50MHz， 入 率 1.123MHz 的 製 參數