数字加网并行加速算法研究与实现.pdfVIP

The 2011 Asia-Pacific Youth Conference of Youth Communication and Technology Research on Parallel Acceleration of Digital Screening Algorithm Lianqing ZHAO, Chang SU , Jinhe LIU, Yuhang CHEN School of Electric and Electronic engineering, North China Electric Power University, Beijing,China Abstract: In contrast with serial processing, parallel computing with reconfigurable processors is more suita- ble for digital screening algorithm. In this paper, taking FS error diffusion algorithm for example, method of parallel implementation of serial algorithm was described in details and the possibility of raising screening speed was analyzed in theory. In the contrast experiments, both serial and parallel computing were imple- mented to get the same set of images in different sizes screened and the results showed that the algorithm par- alleled could effectively raise screening speed, especially for large images, and it could meet the advanced demands for image processing. Keywords: digital screening; algorithm acceleration; parallel computing; error diffusion; FPGA 数字加网并行加速算法的研究和实现 赵莲清，苏畅，刘金荷，陈宇航 华北电力大学 电气与电子工程学院，北京，中国，102206 摘 要:数字加网算法运算重复度高，更适合采用可重构处理器并发执行。本文以 FS 误差扩散算法为 例，探讨了串行算法并行化实现的思路和方法，从理论上分析了加网提速的可行性，并对同一组大小 不同的图像设置对比实验，分别使用串行和并行两种计算方式进行加网。实验结果表明，经改造后的 算法有效地提高了计算速度，对大尺寸图像的加网效率明显提升，能满足更高层次的图像处理需求。 关键字:数字加网；算法加速；并行计算；误差扩散； FPGA 流水化作业方式，充分利用软硬件资源，处理效率很 1 引言 高；性能提升不依赖于硬件性能的提高，扩展性好。 [1] 加网 技术是印刷复制的关键，是直接决定图文 近些年来可重构计算理论飞速发展，并行化处理思想 印刷品还原质量的核心技术。调频加网技术是数字印 深入计算领域，各种 FPGA 结合串行微处理器的数字 刷