Design and Implementation of LowPower DigitSerial Multipliers.pdfVIP

Design and Implementation of LowPower DigitSerial Multipliers YunNan Chang Janardhan H Satyanarayana and Keshab K Parhi Department of Electrical and Computer Engineering University of Minnesota Minneap olis MN USA Email fynchang jsat yana parhi geceumnedu Abstract KHz to MHz Real time implementation of these systems require hardware architectures which can pro Digitserial architectures obtained using traditional cess input signal samples as they are received as op unfolding techniques cannot be pip elined beyond a cer p osed to storing them in registers and pro cessing them tain level because of the pr esence of fe edback loops in batch mo de It is well known that bitserial systems In this p aper a novel design methodology is pr esented which pro cess one bit of the input sample in one clo ck which p ermits bitlevel pip elining of the digitserial ar cycle are areaecient and ideal for lowsp eed appli chitectures This enables bitlevel pip elining of digit cations On the other hand bitparallel systems serial architectures thereby achieving sample speeds which pro cess one whole word of the input sample in close to corresponding bitparal lel multipliers with sig one clo ckcycle are ideal for high sp eed applications nicantly lower area This increased sample speed can However in applications which require mo der be traded with reduction in p ower supply voltage re ate sample rates b oth these systems may b e ineective sulting in signicant reduction in p ower consump