SoC架构下片上总线的研究和设计.pdf

实现一主多从星型拓扑结构，并实现了适合于HDTV SoC 多核系统 的总线架构解决方案。在HDTV SoC 系统的设计过程中，由于采用 了内核复用技术，因此在双处理器或多处理器之间往往存在着复杂的 接口逻辑和时序关系，所以在完成 SoC 系统架构的设计之后，必须 且首先要进行片上总线时序的验证以及相关路径的时序优化。本文依 据X-Bus 总线和HDTV SoC 系统的特性，提出了插入流水线并重新 划分系统模块的方法来改善 SoC 系统的时序性能，以确保系统的性 能验证和功能实现的顺利完成。 最后，文章详细分析和讨论了有关时序验证和优化实现的结果， 其结果表明所提出的系统架构的解决方案以及时序优化措施都具有 良好性能以及适用的可行性。 经过总线的选型和性能优化，X-Bus 总线可作为一种完全满足 HDTV SoC 系统所有既定要求的理想的总线结构。经过优化后的总线 可保证系统验证和实现的正确完成，使得HDTV SoC 作为一个多核 系统能够正确高效地完成双处理器之间的通信。 采用针对HDTV SoC 系统而优化的X-Bus 总线，HDTV SoC 系统 正确地实现了各模块的内部互连，实现了既定功能。验证板的验证也 表明了该系统具备对基于 MPEG-2 标准编码的数字电视信号的实时 解码能力，系统工作频率达到高清数字电视信号108MHz 的实时解码 速率要求，从而具有良好的应用前景。 关键词：X-Bus ， HDTV SoC ， 时序性能优化， FPGA 验证 iv THE DESIGN AND IMPLEMENTATION OF ON-CHIP BUS IN SoC Abstract SoC(System On a Chip) technology has now become leading one on integrated circuit design and application, with the development of the integrated circuit technologies and the improvement of integration degree. More and more system that originally implemented on PCB board would be integrated into one single chip. The typical structure of a SoC is consisted of one or more CPU/DSP, as the embedded processor(s) within this chip, and more functional modules or IP modules. These devices are generally interconnected with the on-chip bus. The architecture, the operating mode and the timing feature of the bus could affect the efficiency of the SoC strongly in this situation. In addition, the integration and the reuse of the IP module also need a high performance on-chip bus. Thus, it is great important for the on-chip bus to be select and design during the SoC’s design. This thesis discusses the on-chip bus used in the HDTV SoC, as well