第4章 状态机设计.ppt

【例】用状态机的方法设计十三进制计数器 library IEEE; use IEEE.std_logic_1164.all; entity counter13 is port(cp:in std_logic; reset:in std_logic; q:out std_logic_vector(3 downto 0); op:out std_logic); end counter13; architecture rt1 of counter13 is type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12); signal presentstate,nextstate:state; signal qn:std_logic_vector(3 downto 0); begin switchtonextstate:process(reset,cp) begin if reset=‘1’ then presentstate=s0; elsif cpevent and cp=1 then presentstate=nextstate; end if; end process switchtonextstate; changestatemodel:process(presentstate) begin case presentstate is when s0=nextstate=s1; qn=0000; op=0; when s1=nextstate=s2; qn=0001; op=0; when s2=nextstate=s3; qn=0010; op=0; when s3=nextstate=s4; qn=0011; op=0; when s4=nextstate=s5; qn=0100; op=0; when s5=nextstate=s6; qn=0101; op=0; when s6=nextstate=s7; qn=0110; op=0; when s7=nextstate=s8; qn=0111; op=0; 设计实例： 设计一个存储控制器，具体要求如下： （1）存储控制器能根据微处理器的读周期或写周期，分别对存储器输出写使能信号we和读使能信号oe; (2)存储控制器的输入信号有3个：微处理器的准备就绪信号ready、读写信号read_write和时钟信号clk. library ieee; use ieee.std_logic_1164.all; entity store_controller4 is port(ready: in std_logic; clk:in std_logic; read_write: in std_logic; we,oe:out std_logic); end store_controller4; architecture state_machine of store_controller4 is type state_type is (idle,decision,read,write); signal present_state,state:state_type:=idle; begin state_transfer3:process(present_state,ready,read_write) begin case present_state is when idle= if(ready=1)then state=decision; else state=idle;