4 combinational logic(修订)研讨.ppt

* * * * * * * For lecture Evaluate transistor, Me, eliminates static power consumption * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Transmission Gate XOR A B F B A B B M1 M2 M3/M4 Dynamic Logic Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors Dynamic Gate In1 In2 PDN In3 Me Mp Clk Clk Out CL Out Clk Clk A B C Mp Me Two phase operation Precharge (CLK = 0) Evaluate (CLK = 1) Dynamic Gate In1 In2 PDN In3 Me Mp Clk Clk Out CL Out Clk Clk A B C Mp Me Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 off on ((AB)+C) Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities extra load on Clk PDN starts to work as soon as the inp