xiti1.pptVIP

1、写出下列缩写的中文（或者英文）含义 VHDL: 超高速集成电路硬件描述语言 FPGA:现场可编程门阵列 ASIC:专用集成电路 EDA:电子设计自动化 CPLD：复杂可编程逻辑器件 IP：知识产权核（软件包） HDL：硬件描述语言 2、试描述一个带进位输入、输出的8位全加器 端口：A、B为加数，CIN为进位输入，S为加和，COUT为进位输出。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADDER8 IS PORT (A, B : IN STD_LOGIC_VECTOR (7 DOWNTO 0); CIN : IN STD_LOGIC; COUT : OUT STD_LOGIC; S : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END ADDER8; ARCHITECTURE ONE OF ADDER8 IS SIGNAL TS : STD_LOGIC_VECTOR (8 DOWNTO 0); BEGIN TS = (‘0’ A) + (‘0’ B) + CIN; S = TS(7 DOWNTO 0); COUT = TS(8); END ONE; 3、设计一数据选择器MUX,其系统模块图和功能表如下图所示。试采用下面三种方式中的两种来描述该数据选择器MUX的结构体。 (a) 用if语句。 　(b) 用case 语句。 　(c) 用when else 语句。 Library ieee; Use ieee.std_logic_1164.all; Entity mymux is Port ( sel : in std_logic_vector(1 downto 0); Ain, Bin : in std_logic_vector(1 downto 0); Cout : out std_logic_vector(1 downto 0) ); End mymux; Architecture one of mymux is Begin Process (sel, ain, bin) Begin If sel = “00” then cout = ain or bin; Elsif sel = “01” then cout = ain xor bin; Elsif sel = “10” then cout = ain and bin; Else cout = ain nor bin; End if; End process; End one; Architecture two of mymux is Begin Process (sel, ain, bin) Begin Case sel is when “00” = cout = ain or bin; when “01” = cout = ain xor bin; when “10” = cout = ain and bin; when others = cout = ain nor bin; End case; End process; End two; Architecture three of mymux is Begin Cout = ain or bin when sel = “00” else Ain xor bin when sel = “01” else Ain and bin when sel = “10” else ain nor bin; End three; 4、综合题 Library ieee; Use ieee.std_logic_1164.all; Entity mooreb is Port (clk, reset : in std_logic; Ina : in std_logic_vector (1 downto 0); Outa : out std_logic_vector (3 downto 0) ); End mooreb; Architecture one of mooreb is Type ms_state is (st0, st1, st2, st3); Signal c_st, n_st : ms_state; Begin Process (clk, reset) Begin If reset = ‘1’ then c_st = st0; Elsif clk’event and clk = ‘1’ then c_st =