Lec05(数字电路第五节).pptVIP

Jin. UESTC Digital Logic Design and ApplicationJin YanhuaLecture #5 CMOS Steady-State Electrical Behavior Last Time Positive Logic and Negative Logic Logic Families: TTL and CMOS Logic Family CMOS Logic Level Last Time Last Time Last Time 3.4 Electrical Behavior of CMOS Circuits Digital analysis works only if circuits are operated in specification: Power supply voltage Temperature Input-signal quality Output loading Must do some “analog” analysis to prove that circuits are operated in spec. Fan-out specs Timing analysis (setup and hold times) 3.4 Electrical Behavior of CMOS Circuits Data Sheets and Specifications (P99 Table 3-3) 3.5 CMOS Steady-State Electrical Behavior 3.5.1 Logic Levels and Noise Margins 3.5 CMOS Steady-State Electrical Behavior Logic Levels Specifications 3.5 CMOS Steady-State Electrical Behavior 5.3.2 Circuit Behavior with Resistive Loads Output-voltage drop Resistance of “off” transistor is 1 Megohm, but resistance of “on” transistor is nonzero, Voltage drops across “on” transistor, V = IR For “CMOS” loads, current and voltage drop are negligible. For TTL inputs, LEDs terminations, or other resistive loads, current and voltage drop are significant and must be calculated. 3.5.3 Circuit Behavior with Nonideal Inputs 3.5.4 Fanout The number of inputs that the gate can drive without exceeding its worst-case loading specifications. Fanout must be examined for both possible output states, HIGN and LOW. overall fanout = min (HIGH-state, LOW-state fanout) DC fanout and AC fanout 3.5.5 Effects of Loading Loading an output beyond its rated(额定的) fanout has several effects: (P111) The output voltage may deteriorate. The propagation delay, output rise and fall time may increase beyond their specifications. The operating temperature of the device may increase, thereby reducing reliability and causing device failure. 3.5.6 Unused Inputs Unused CMOS input should never be left unconnected (or floating). 3.6 CMOS Dynamic Electrical Behavior