010- A to D Converter.pptVIP

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010- A to D Converter.ppt

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Analog to Digital Converter A/D RegisterMap A/D Clock Select/ Prescaler Conversion Timing A/D Control Registers (Cont’d) Result Registers SCF - Sequence Complete Flag - Set at end of conversion sequence in single conversion mode (SCAN = 0) and at the end of first conversion sequence in continuous conversion mode (SCAN = 1). - A write to this register clears SCF flag when (AFFC = 0). ETORF - External Trigger Overrun Flag -Sets if active edges occur while conversion sequence in progress. FIFOR - Sets when the Result Register has been written before it was read by the CPU ( CCF was not cleared). CC[2:0] - Conversion Counter 3-Bit counter that points to the next channel to be converted in 4 or 8 count sequence. CCF7 -CCF0 - Conversion Complete Flags for individual A/D channels. - Set upon end-of-conversion for each associated A/D channel. - Cleared when associated A/D result register is read. A/D Port Register HCS12 Technical Training, Rev 2.0 Module 10- A/D Converter, Slide * MOTOROLA and the Stylized M Logo are registered in the US Patent Trademark Office. All other product or service names are the property of their respective owners. ? Motorola, Inc. 2001. ANALOG TO DIGITAL CONVERTER (ATD) Internal Bus SCI 1 256K FLASEEPROM 12K SRAM ATD 1 HCS12 CPU BKP INT MMI CM BDM MEBI 4K BYTES EEPROM SIM msCAN 3 msCAN 2 msCAN 1 SCI 1 SPI 2 or PWM CH 4-7 BDLC or msCAN 0 msCAN 4 or IIC SPI 1 or PWM CH 0-3 SPI 0 ATD 0 PIM PLL PIT ECT 8 CHAN PWM 8 CHAN FEATURES: ? 8/10 Bit Resolution. ? 7 usec, 10-Bit Single Conversion Time. ? Sample Buffer Amplifier. ? Programmable Sample Time. ? Left/Right Justified, Signed/Unsigned Result Data. ? External Trigger Control. ? Conversion Completion Interrupt Generation. ? Analog Input Multiplexer for 8 Analog Input Channels. ? Analog/Digital Input Pin Multiplexing. ? 1 to 8 Conversion Sequence Lengths. ? C