超大CMOS集成电路原理chapter7.pptVIP

Digital Integrated CircuitsA Design Perspective Sequential Logic Naming Conventions In our text: a latch is level sensitive a register is edge-triggered There are many different naming conventions For instance, many books call edge-triggered elements flip-flops This leads to confusion however Latch versus Register Latches Latch-Based Design Timing Definitions Characterizing Timing Maximum Clock Frequency Positive Feedback: Bi-Stability Meta-Stability Writing into a Static Latch Mux-Based Latches Mux-Based Latch Mux-Based Latch Master-Slave (Edge-Triggered) Register Master-Slave Register Clk-Q Delay Setup Time Reduced Clock Load Master-Slave Register Avoiding Clock Overlap Overpowering the Feedback Loop ─Cross-Coupled Pairs Cross-Coupled NAND Sizing Issues Storage Mechanisms Making a Dynamic Latch Pseudo-Static More Precise Setup Time Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Setup/Hold Time Illustrations Other Latches/Registers: C2MOS Insensitive to Clock-Overlap Pipelining Other Latches/Registers: TSPC Including Logic in TSPC TSPC Register Pulse-Triggered LatchesAn Alternative Approach Pulsed Latches Pulsed Latches Hybrid Latch-FF Timing Latch-Based Pipeline Non-Bistable Sequential Circuits─Schmitt Trigger Noise Suppression using Schmitt Trigger CMOS Schmitt Trigger Schmitt Trigger Simulated VTC CMOS Schmitt Trigger (2) Multivibrator Circuits Transition-Triggered Monostable Monostable Trigger (RC-based) Astable Multivibrators (Oscillators) Relaxation Oscillator Voltage Controller Oscillator (VCO) Differential Delay Element and VCO Circuit before clock arrival (Setup-1 case) Hold-1 case 0 Hold-1 case 0 Hold-1 case 0 Hold-1 case 0 Hold-1 case 0 “Keepers” can be added to make circuit pseudo-static M 1 D Q M 4 M 2 0 0 V DD X M 5 M 8 M 6