高性能Memory+BIST设计实例论文.docxVIP

高性能 Memory BIST 设计实例摘要随着 SoC 设计向存储器比例大于逻辑部分比例的方向发展，高质量的存储器测试策略显得尤为重要。存储器内置自测试(BIST)技术以合理的面积开销来对单个嵌入式存储器进行彻底的测试，可提高产品质量及合格率，因此正成为测试嵌入式存储器的标准技术。然而，随着存储器性能的提升，对全速测试(at-speed test)BIST 电路的设计提出了越来越高的要求。本文提出了一种基于有限状态机 FSM（Finite State Machine）的 BIST 优化方案。优化后的电路无论在速度和面积开销上都比传统的设计结构获得了显著的性能提升。关键词：SoC 设计；BIST；March；FSMONE EXAMPLE OF HIGH PERFORMANCE MEMORYBIST DESIGHABSTRACTAs the area ratio of embedded memory versus logic circuit in aSOC design increases, a high quality memory test methodology becomesextremely important. Memory Built-In Self-Test (BIST) technology hasbeen the standard memory test methodology, since it can test singlememory with high coverage to enhance product quality and yield, with areasonable area overhead. The high performance memory brings up thechallenge to BIST circuit design for at-speed test. The paper proposes anFSM structure optimization method. The optimized BIST circuitachieves better speed and area performance than the traditional designs.KEY WORDS: SoC design; BIST; March; FSM图片目录图 1：SoC 中存储器的使用情况 ············································································· 2图 2：芯片缺陷分类 ································································································ 2图 3 Memory BIST 的应用结构 ··············································································· 3图 4 用于嵌入式存储器的 BIST 电路 ····································································· 5图 5 MBIST 电路概述 ······························································································ 5图 6 采用比较器实现的 MBIST 电路······································································ 6图 7 采用 MISR 压缩器实现的 MBIST 电路 ·························································· 6图 8 全速存储器 BIST 流水线 ················································································· 7图 9 基于 FSM 状态机的存储器内置自测试 MBIST 系统 ·································· 12图 10 多个测试算法模块并行结构 ········································································ 13图 11 扫描链旁路单元··········