VSIPL+ FPGA Design MethodologyVSIPL FPGA的设计方法.pptVIP

VSIPL++ / FPGA Design Methodology Capt. Jules Bergmann, AFRL/IFTC Susan Emeny, ITT Peter Bronowicz, ITT Overview Introduction- Designing for Hybrid Architectures Design Methodology VSIPL++ / FPGA Integration Integration and Test Applications Status Future Work Conclusions Introduction Hybrid Computer Architectures FPGAs and Programmable Processors have the potential to deliver high performance Commercially Available Challenge of hybrid architectures to develop a methodology that will: Exploit their capabilities effectively while Making FPGAs accessible to a larger community of developers. Requirements Requirements of the Methodology Hardware Software development needs to begin early Portable from test to final system, minimal change Scalable to future technologies, minimal change Productive Concise function description for both HW SW Streamlined interface between HW SW Use existing hardware and software methodologies Design Methodology Algorithm High level exploration (Matlab) Software Scalar, C++, VSIPL++ Performance Imp. (parallel) Hardware VHDL FPGA Performance libraries Integration HW/SW Debug on commodity cluster Migrate to target system Benefits of the Methodology Support for System Design from algorithm to embedded system Simplifies integration of hardware and software Application acceleration via pre-defined FPGA libraries Standard functions (fft) Custom Hardware Design Methodology Portability Scalability Use standard high level synthesis (RTL) Performance Encapsulate device specific optimizations in macro cells Productivity Standardize interface between units for data exchange Use stream interface with flow control. This model matches the way data is usually produced from sensors and requires minimal assumptions about environment Commodity Hardware Software Design Methodology VSIPL++ was chosen to achieve: Portability, the reference version compiles anywhere! Scalability, builds on existing standards i.e.. MPI Performance Allows for optimized