Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology英文文献资料.docVIP

Circuits and Systems, 2011, 2, 326-329 doi:10.4236/cs.2011.24045 Published Online October 2011 (/journal/cs) Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology Shilpi Birla , Neeraj Kumar Shukla , Kapil Rathi , Rakesh Kumar Singh , Manisha Pattanaik 1* 2 3 4 5 1 Department of Electronics Communications, Sir Padampat Singhania University, Udaipur, India Department of ECE, ITM University, Gurgaon, India Texas Instruments, Bangalore, India Department of Electronics Communications, Bipin Chandra Tripathi kumaon Engineering College, Almora, India VLSI Group, Atal Bihari Vajpayee Indian Institute of Information Technology and Management, Gwalior, India E-mail: Received June 7, 2011; revised July 22, 2011; accepted July 29, 2011 2 3 4 5 * shilpibirla@ Abstract In Present scenario battery-powered hand-held multimedia systems become popular. The power consumption in these devices is a major concern these days for its long operational life. Although various techniques to reduce the power dissipation has been developed. The most adopted method is to lower the supply voltage. But lowering the Vdd reduces the gate current much more rapidly than the sub-threshold current and degrades the SNM. This degraded SNM further limits the voltage scaling. To improve the stability of the SRAM cell topology of the conventional 6T Static Random Access Memory (SRAM) cell has been changed and revised to 8T and 10T cell, the topologies. This work has analyzed the SRAM’s Static Noise Margin (SNM) at 8T for various process corners at 65 nm technology. It evaluates the SNM along with the write margins of the cell along with the cell size of 8T SRAM bit-cell operating in sub-threshold voltage at various process cor- ners. It is observed that an 8T