Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks 英文参考文献.docVIP

Sensors 2012, 12, 2667-2692; doi:10.3390/s120302667 OPEN ACCESS sensors ISSN 1424-8220 /journal/sensors Article Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks Juan Valverde *, Andres Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre and Teresa Riesgo Centro de Electronica Industrial, Universidad Politecnica de Madrid, Jose Gutierrez Abascal 2, Madrid 28006, Spain; E-Mails: joseandres.otero@upm.es (A.O.); miguel.lopezl@alumnos.upm.es (M.L.); jorge.portilla@upm.es (J.P.); eduardo.delatorre@upm.es (E.T.); teresa.riesgo@upm.es (T.R.) * Author to whom correspondence should be addressed; E-Mail: juan.valverde@upm.es; Tel.: +34-913-363-191; Fax: +34-915-645-966. Received: 2 December 2011; in revised form: 23 December 2011 / Accepted: 22 February 2012 / Published: 28 February 2012 Abstract: While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the pa