实验2-3. 移位运算器实验.pdf

实验2-3. 移位运算器实验 程序设计与硬件实验 K 康芯科技 X 实验2-3.移位运算器实验 K 键5控制时钟 S、M共同控制移位模式 键6控制S 计数器产生2位移位控制模式码 键2/1输入待移位数据 K 康芯科技 X K Library IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SHEFT IS PORT (CLK,M,C0 : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CN : OUT STD_LOGIC ; SD : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY; ARCHITECTURE BEHAV OF SHEFT IS 2 、然后选择M=0 、S=10，SM=2： SIGNAL ABC : STD_LOGIC_VECTOR(2 DOWNTO 0); 选通循环左移操作 SIGNAL REG : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL SM : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL CY : STD_LOGIC ; BEGIN PROCESS (CLK,SM,C0) BEGIN IF CLKEVENT AND CLK = 1 THEN CASE SM IS WHEN 011 = REG(0) = C0 ; REG(7 DOWNTO 1) = REG(6 DOWNTO 0); CY = REG(7); --带进位循环左移 WHEN 010 = REG(0) = REG(7); REG(7 DOWNTO 1) = REG(6 DOWNTO 0); --循环左移 WHEN 100 = REG(7) = REG(0); REG(6 DOWNTO 0) = REG(7 DOWNTO 1); --循环右移 WHEN 101 = REG(7) = C0 ; REG(6 DOWNTO 0) = REG(7 DOWNTO 1); CY = REG(0); --带进位循环右移 WHEN 110 = REG(7 DOWNTO 0) =