FPGA实验报告精选.docVIP

FPGA实验上机报告 实验二 Part1代码 运行结果拨码开关控制Nice 代码 运行结果拨码开关控制数码管显示数字 （1）watch.vhd： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -----This is a simple watch with sec/min/hour display in DE2 broad -----SW(0) is the reset input, when SW(0)=1,the program runs. ENTITY watch IS PORT(SW: IN STD_LOGIC_VECTOR(17 DOWNTO 0); clk_50:IN STD_LOGIC; HEX0:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX1:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX2:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX3:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX4:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX5:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX6:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); HEX7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END watch; -------------------------------------------------- ARCHITECTURE rtl OF watch IS COMPONENT sec_clk IS -----create a clk signal 1Hz frequency PORT(clk_50 :IN STD_LOGIC; clk_div1 :OUT STD_LOGIC); END COMPONENT; COMPONENT count4 IS -----second counter PORT(res,stop,clk :IN STD_LOGIC; ca :OUT STD_LOGIC; --ca=1 when second count=59 a :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT count3 IS -----second counter PORT(res,clk :IN STD_LOGIC; ca :OUT STD_LOGIC; --ca=1 when second count=59 a:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT seccount IS -----second counter PORT(res,clk :IN STD_LOGIC; ca :OUT STD_LOGIC; --ca=1 when second count=59 a,b :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT mincount IS PORT(en,res,clk:IN STD_LOGIC; ca:OUT STD_LOGIC; a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT count24 IS PORT(en,res,clk:IN STD_LOGIC; a,b:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT; COMPONENT dis IS PORT(d:IN STD_LOGIC_VECTOR(3 DOWNTO 0); q:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END COMPONENT; SIGNAL stop: STD_LOGIC:=0; SIGNAL res: STD_LOGIC:=0; SIGNAL sec1: STD_LOGIC:=0; SIGNAL t1: STD_LOGIC:=0; SIGNAL m