COA课件15.ppt

Interrupt cycle t1: Acknowledge - IRQ t2: Interrupt Number - MBR 确定身份 t3: (MBR) - IR (SP)-MAR t4: (PC)-MBR t5: (MAR)-Memory 保护返回地址 (MBR)-Memory write-Memory t6: (IR)-MAR (SP)-1-SP ( SP always points to t7: (MAR)-Memory an empty location read-Memory as top of stack ) t8：Memory-MBR t9: (MBR)-PC 获得ISR的入口地址 Design of control unit Step1: CPU Structure (ALU,Registers,Bus/PathwayGate) Step2: Instruction Set (List of all instructions) Step3: Micro_operations Step4: Control Signals Step5: Make out the relationship of control signals Step6: Digital Circuit Design Step7: Hardware §15.2 Control unit’s Functional Requirements Define basic elements of processor Describe micro-operations processor performs (information flows ) Describe paths of information flow gates on paths Determine functions that control unit must perform(control signals that operate the gates) Basic Elements of Processor ALU Registers Internal data paths External data paths Control Unit Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops Functions of Control Unit Sequencing 先后顺序 Causing the CPU to step through a series of micro-operations Execution 执行 Causing the performance of each micro-op This is done using Control Signals Control Signals - input(1) Clock One micro-instruction (or set of parallel micro-instructions) per clock cycle. e.g. t1, t2, t3, … Instruction register Op-code for current instruction Determines which micro-instructions are performed during the execute cycle Control Signals - input (2) Flags State of CPU Results of previous operations From control bus Interrupt request signals Control Signals - output Within CPU(two types) Cause data movement Activate specific functions(e.g. add/sub/…) Control signal to control bus To memory(e.g. read/write) To I/O modules