吞吐量和延时约束下的片上通信结构的Pareto空间优化.pdfVIP

计算机研究与发展 ISSN 1000-1239!CN 11-l777!TP Journal of Computer Research and Development 46(Supp l. ): 360-364. 2009 吞吐量和延时约束下的片上通信结构的 Pareto 空间优化 曹亚非王大伟李思昆 (国防科学技术大学计算机学院 长沙 410073) (yfcao@nudt. edu. cn) Pareto Space Optimization for Throughput and Delay Constrained on-Chip- Communication Architectures Cao Yafei , Wang Dawei , and Li Sikun (College of Computer. National University of Defense Technology , Changsha 410073) Abstract The performance of SoC depends mainly on the interconnect architecture of IP cores. Recently , the configuration and optimization of on-chip-communication architectures become hot and popular , while existing methods still have some disadvantages of low simulation speed and poor design space exploration. Besides. mostly used single objective optimization cannot resolve the conflict of multiple performance objectives. An automatic Pareto space optimization approach is put forward for throughput and delay constrained on-chip-communication architectures , which uses on-chip communication architecture template , transaction level communication simulation and evolutionary multi-objective optimization algorithm to explore the Pareto space with throughput and delay constraints. Experiments show that the approach effectively improves the quality and the speed of optimizing SoC communication architecture. which improves the throughput by 10% and reduce the transfer delay by 17 % compared with that of Srinivasan. Key words system on chip; on-chip-communication; evolutionary multi-objective optimization algorithm; bus configuration space; transaction level simulation 摘要 SoC 中各 IP 核之间的互连结构是决定片上系统，性能的关键因素.近年来，片上互连通信结构的 配置与优化成为 SoC 通信综合的研究重点和热点，而已有方法优化 SoC 互连通信结构的仿真速度较 慢，支持设计自动化的能力较差，使用的单目标优化算法无法解决多个性能目标之