应用新技能 设计PCB时抗静电放电的方法(国外英文资料).doc

使用新技巧 设计PCB时抗静电放电的方法(国外英文资料) This article is contributed by jimoom DOC documents may experience poor browsing on the WAP side. It is recommended that you first select TXT, or download the source file to the local view. In the design of the PCB board, the anti ESD design of PCB can be realized through layering, proper layout, routing and installation. By adjusting the layout and wiring of PCB, ESD can be well protected. * multilayer PCB is used as far as possible, compared with double PCB, ground plane and power plane, and closely spaced signal earth line spacing can reduce common mode impedance and inductive coupling, so as to achieve the double PCB 1/10 to 1/100. For the top and bottom surfaces, there are components with short connections. From human, environment and even electronic equipment for electrostatic semiconductor chip precision will cause various injuries, such as through the internal components of thin insulating layer; a gate MOSFET lesion and CMOS components in the CMOS device; trigger lock; short PN junction reverse biased p-n junction is short; the bias; melting active devices in welding wire or wire. In order to eliminate the interference and damage of electrostatic discharge (ESD) to electronic equipment, a variety of technical measures should be taken to prevent it. In the design of the PCB board, the anti ESD design of PCB can be realized through layering, proper layout, routing and installation. In the design process, the majority of the design changes can be limited to components only through prediction. By adjusting the layout and wiring of PCB, ESD can be well protected. Here are some common precautions. * multilayer PCB is used as far as possible, compared with double PCB, ground plane and power plane, and the signal line of closely spaced wire spacing can reduce common mode impedance and inductive coupling, so as to achieve the double PCB 1/10 to 1/100. Signal each signal layer as close as possible to a power or ground layer. For the top