拉扎维《模拟集成电路设计》第二版课件 ch9.pptVIP

* Example 9.21 For the below design explain why the output CM level is inevitably well below VDD/2 and hence the output swings are limited. Devise a solution. Solution: The output CM is equal to VG7,8, which is only slightly greater than one threshold. The issue can be resolved by drawing a small current from node Q. It can be upwards to desired output and the device is still in saturation. * CMFB for Cascode First Stage First stage use deep triode feedback loop to avoid loading. Achieving high gain while not precise * Input Range Limitations Input common-mode level may need to vary over a wide range, e.g. ADC input comparator. Input swing limits the total range sometimes. In the below single-end unity-gain buffer the input CM minimal voltage is VGS1,2+VISS, which is one threshold greater than 2Vov in the output CM. * Extension of Input Range Incorporate both NMOS and PMOS differential pair to keep a necessary transconductance The transconductance variation should be concerned Gain, speed and noise may vary * Slew Rate In a linear circuit, the slope of the step depends on final output value The observation applies to linear feedback system * Slew Rate In a realistic case, with large input steps, the output displays a linear ramp having a constant slope. The slope of ramp is the “slew rate”. It seems that the maximum current to charge the load capacitance is limited. Nonlinear behavior. Reduce speed and increase distortion. Increase SR would consume power and wider device * Slew Rate Example A small step rises Vout by and hence adjusts through R1, R2 negative feedback circuit. When M1 experiences a large step, M2 turns off. Thus, CL is charged by a constant current ISS. Feedback is broken but after M2 turns on, the circuit returns to a linear operation. * Example 9.22 (a)Determine the small-signal step response of the circuit. (b)Calculate the positive and negative slew rates. Solution: * Slew Rate of Te