Wallace树乘法器.pdfVIP

34 17 2008 9 Vol.34 No.17 Computer Engineering September 2008 ·· 2008 A TP303 Wallace 32 ( 450004) 3 Booth Wallace LING FPGA 0.18 µm SMIC Wallace 29%17%38% Booth Wallace LING Low-power 32-bit Multiplier Based on Leapfrog Wallace Tree LI Wei, DAI Zi-bin, CHEN Tao (Institute of Electronic Technology, PLA Information Engineering University, Zhengzhou 450004) AbstractIn order to improve performance of multiplier, this paper adopts modified Booth algorithm to generate partial product, proposes the leapfrog Wallace tree architecture to compress partial product, and introduces the modified LING adder to compute the final sum of the result of Wallace tree. The design is realized by using Altera’s FPGA. Synthesis, placement and routing of 32-bit multiplier are accomplished on 0.18 µm SMIC process. Compared with conventional multiplier with traditional Wallace tree, the multiplier reduces the multiplication time, the power dissipation and the area of multiplier by 29%, 38% and 17%. Key wordsBooth algorithm; leapfrog Wallace tree; multiplier; LING adder 1 Booth CPU CPU 0.18 µm SIMC CPU[1] ( BoothBooth 3M, 5M, 6M, 7M) Booth4 8 Booth 3M, 5M, 6M, 7M [2] [3] 3M Wallace LING 3 Booth