电子科技大学《数字逻辑设计及应用》Lec17-Chap 7.pptVIP

* Summaries of Latch and Flip-Flop Latch: output changes when CLK is asserted Flip-Flop: output only changes when clock changes S-R Latch/FF, D Latch/FF, J-K FF, T FF Logic Symbol Function Table Transition Table Characteristic Equ. Excitation tables State Diagram EN Jin. UESTC Digital Logic Design and Application * Digital Logic Design and ApplicatonLecture #17 Latches and Flip-Flops UESTC, Spring 2013 * 再谈串行输入加法器的实现 Q D Q C X Y CI Si Ci+1 Xi Yi Ci S CO CLK 暂存 X Y CI CO S Ci+1 Si Xi Yi Ci 时钟控制 电平有效还是边沿有效？ 串行输入、串行输出 注意：时钟同步 Iterative Vs. Sequential * Iterative Versus Sequential Circuits C0 C4 X0 Y0 X1 Y1 X2 Y2 X3 Y3 S0 S1 S2 S3 * 7.2 Latches and Flip-Flops Latches change its outputs at any time (enable input is asserted). Flip-Flops change its outputs only when the clock changes CLK Positive-Edge Rising-Edge Negative-dge Falling-Edge Level triggered Edge-triggered, ET * 7.2.5 Edge-Triggered D Flip-Flops D Q C Q D Q C Q Q QL D CLK master slave Qm When CLK=0, When CLK=1, Qm follows D; Q is unchanging. Qm is unchanging, Q = Qm until the next rising CLK edge 1. Master/Slave, Positive-edge-triggered Q changes only when CLK rises from 0 to 1 * Timing Diagram for master-slave D F/F D CLK Q Qm D Q C Q D Q C Q Q QL D CLK Qm Q =D( ) * D CLK Q D Q CLK Q Logic Symbol Edge-Triggered * D CLK Q D CLK Q D Latch D Flip-Flop —— edge-triggered when CLK is asserted 对信号扰动不敏感 受信号扰动影响 * D flip-flop timing parameters Propagation delay ( from CLK ) tpLH(CQ) tpHL(CQ) tsetup 建立时间 thold 保持时间 Setup time ( D before CLK） Hold time ( D after CLK) D CLK Q 在时钟上升边沿附近有一个时间窗口，在此窗口时间内，数据输入D不能改变，否则电路进入亚稳态。 从输入信号D到来时刻至信号D 达到稳定所持续的时间。 从输入信号D达到稳定至信号D 被锁存器接受所持续的时间。 * 2. Negative-Edge-Trigged D Flip-Flop D Q C Q D Q C Q Q QN D CLK D Q CLK Q D Q C Q D Q C Q Q QL D CLK Positive-edge-triggered 3. D Flip-Flop with preset and clear 同步(synchronous)是指与时钟同步，即时