《Electronic Circuit Design1模拟电子技术》L11_07 MOSFETs 1 - Introduction.pptVIP

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《Electronic Circuit Design1模拟电子技术》L11_07 MOSFETs 1 - Introduction.ppt

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Flow Control Model Flow Control Model Flow Control Model The FET Family Tree The FET Family Tree The FET Family Tree The FET Family Tree Metal Oxide Silicon FET (MOSFET) MOS Capacitor ‘Sandwich’ construction 2 conducting plates + dielectric ‘filling’ Upper conducting plate - polysilicon (Gate) Lower conducting plate - silicon (Substrate) Insulating dielectric - silicon dioxide (Gate Oxide) The MOS Capacitor MOSFET Construction Source and Drain implants are placed one on either side of the MOS ‘sandwich’ source and drain are n-type (for an n-channel MOSFET) or p-type (for a p-channel MOSFET) source and drain doping is opposite polarity to that of the substrate The region underneath the gate oxide between the source and drain is called the Channel MOS Transistor (MOSFET) MOS Transistor Operation Channel is normally non-conducting (open-circuit): No bias voltage (or small voltage) applied to Gate Source and Drain junctions are reverse-biased relative to the substrate Depletion regions surround the Source and Drain Channel is depleted of mobile charge carriers Channel starts to conduct when: Gate voltage VGS exceeds the Threshold Voltage VT Mobile charge is present in the channel MOSFET Operation 0 VGS VT Channel in Depletion Majority carriers in p-type substrate (holes) are repelled by positive charge on the Gate No current flows in the channel VGS 3 VT Channel in Inversion Electrons (minority carriers in substrate) are drawn into channel by positive charge on the Gate Current flows in the channel MOSFET Circuit Symbols N-Channel MOSFET Transfer Characteristic 0 2.5 5 0 2.5 5 0 2.5 5 POLYSILICON GATE ELECTRODE IMPURITY-DOPED CRYSTALLINE SILICON SUBSTRATE GATE OXIDE (SiO2) n+ n+ p- SOURCE DRAIN GATE SUBSTRATE GATE OXIDE CHANNEL p Substrate S D G VDS + _ Source Depletion Region Drain Depletion Region mA IDS = 0 n+ n+ B p Substrate S D G VDS + _ mA VGS VT + _ Channel in Depletion IDS = 0 n+ n+ B p Substrate S D G VDS + _ mA VGS 3 VT + _ Channel in Inversion IDS 1 0 n+