self-checking synchronous fsm network design with low overhead自检同步fsm网络设计较低的开销.pdfVIP

VLSI DESIGN (C) 2000 OPA (Overseas Publishers Association) N.V. 2000, Vol. 11, No. 1, pp. 47-58 Published by license under Reprints available directly from the publisher the Gordon and Breach Science Photocopying permitted by license only Publishers imprint. Printed in Malaysia. Self-checking Synchronous FSM Network Design with Low Overhead A. Yu. MATROSOVAa’*, I. LEVINb’t and S. A. OSTANINa’* Tomsk State University, Russia; b Tel Aviv University, Israel (Received April 1999; Infinal form 5 October 1999) A method of a self-checking synchronous Finite State Machine (FSM)network design with low overhead is developed. Checkers are used only for FSMs, which output lines are at the same time output lines of the network. The checkers observe output lines of these FSMs. The method is based on reducing the problem to a self-checking synchron- ous FSM design. The latter is provided by applying a special description of FSM namely, so-called unate Programmable Logic Array u) description. Single stuck-at (PLA fault on the FSMpoles and gate poles are considered. PLA realization of FSM allows a factorized or multilevel logic synthesis. The