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simultaneous buffer-sizing and wire-sizing for clock trees based on lagrangian relaxation同时buffer-sizing基于拉格朗日松弛和wire-sizing时钟树.pdfVIP

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simultaneous buffer-sizing and wire-sizing for clock trees based on lagrangian relaxation同时buffer-sizing基于拉格朗日松弛和wire-sizing时钟树.pdf

    simultaneous buffer-sizing and wire-sizing for clock trees based on lagrangian relaxation同时buffer-sizing基于拉格朗日松弛和wire-sizing时钟树

    VLSI Design, 2002 Vol. 15 (3), pp. 587–594 Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation a a, b c YU-MIN LEE , CHARLIE CHUNG-PING CHEN *, YAO-WEN CHANG and D.F. WONG aDepartment of Electrical and Computer Engineering, University of Wisconsin, Madison, WI 53706, USA; bDepartment of Electrical Engineering, National Taiwan University

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