the coarse-grainedfine-grained logic interface in fpgas with embedded floating-point arithmetic unitscoarse-grainedfine-grained逻辑接口与嵌入式fpga浮点运算单元.pdfVIP

Hindawi Publishing Corporation International Journal of Reconfigurable Computing Volume 2008, Article ID 736203, 10 pages doi:10.1155/2008/736203 Research Article The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units Chi Wai Yu,1 Julien Lamoureux,2 Steven J. E. Wilton,2 Philip H. W. Leong,3 and Wayne Luk1 1 Department of Computing, Imperial College London, London SW7 2AZ, UK 2 Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, Canada V6T1Z4 3 Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong Correspondence should be addressed to Chi Wai Yu, cyu@doc.ic.ac.uk Received 7 July 2008; Accepted 30 October 2008 Recommended by Gustavo Sutter This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used. Copyright © 2008 Chi Wai Yu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits un