CDCM1804RGET;CDCM1804RGER;CDCM1804RGERG4;SN0305042RTHR;CDCM1804RGETG4;中文规格书,Datasheet资料.pdfVIP

CDCM1804 SCAS697E – JULY 2003 – REVISED MAY 2005 1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER FEATURES The CDCM1804 is characterized for operation from –40°C to 85°C. • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and For use in single-ended driver applications, the One LVCMOS Single-Ended Output CDCM1804 also provides a VBB output terminal that • Programmable Output Divider for Two can be directly connected to the unused input as a common-mode voltage reference. LVPECL Outputs and LVCMOS Output • Low-Output Skew 15 ps (Typical) for RGE PACKAGE Clock-Distribution Applications for LVPECL (TOP VIEW) Outputs; 1.6-ns Output Skew Between 0 0 D D LVCMOS and LVPECL Transitions Minimizing 2 D 0 0 D 1 S V Y Y V S Noise • VCC Range 3 V–3.6 V 24 23 22 21 20 19 • Signaling Rate Up