没有奇偶校验的,50M时钟,固定115200波特的试验代码.docVIP

没有奇偶校验的，50M时钟，固定115200波特的试验代码 原创经过实际硬件运行过的FPGA 串口基本功能,输入50MHz时钟,波特115200，演示功能会吧串口RX收到的数据从TX输出两次,对其他时钟和波特要换参数 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SERIAL is Port ( clk,exreset,rx :in STD_LOGIC; datain:in STD_LOGIC_vector(15 downto 0); sendfinish,rxtest1 :buffer STD_LOGIC; rxbuf:buffer std_logic_vector(7 downto 0); tx,receivesuccess,stopbiterr,clkrxouttest,rxtest: out STD_LOGIC); end SERIAL; architecture Behavioral of SERIAL is TYPE sreg IS (ready,startbitpending,startbitsure,receive); signal sendprocess,serialtxclk,serialrxclk,success:STD_LOGIC; signal clktxcount,overcount :integer range 0 to 511; signal txbitcount,pendingcount:integer range 0 to 31; signal shiftcount:integer range 0 to 15; signal txshift:STD_LOGIC_vector(15 downto 0); signal rxbitcount,clkrxcount,t2,t3,t4,t5:integer range 0 to 127; signal bittemp:integer range 0 to 3; signal rxshift:std_logic_vector(7 downto 0); signal currentstate,nextstate:sreg; begin serialtxclkout:process(exreset,clk) begin if exreset=0 then clktxcount=0; serialtxclk=1; elsif rising_edge(clk) then if clktxcount=433 then --if clktxcount=3 then clktxcount=0; serialtxclk=1; else clktxcount=clktxcount+1; if clktxcount=216 then --if clktxcount=1 then serialtxclk=0; end if; end if; end if; end process serialtxclkout; serialrxclkout:process(exreset,clk) begin if exreset=0 then clkrxcount=0; clkrxouttest=1; serialrxclk=1; elsif rising_edge(clk) then if clkrxcount=61 then clkrxcount=0; clkrxouttest=1; serialrxclk=1; else clkrxcount=clkrxcount+1; if clkrxcount=30 then serialrxclk=0; clkrxouttest=0; end if; end if; end if; end process serialrxclkout; rxin:process(exreset,serialrxclk) begin if exreset=0 then overcount=0; currentstate=ready; nextstate=ready; pendingcount=0; rxbitcount=0; success=0; elsif rising_edge(serialrxclk) then if sendfinish=0 then success=0; end if; if overcount70 then