双语课件（第7章） 7. Testing logic circuits 《数字设计基础（双语教学版）》Barry Wilknson 教学课件.pptVIP

7.4 Testing sequential circuits The boundary scan output of one chip connects to the boundary scan input of the next chip to form a long shift register. Chips can be individually disabled from the test by having a selectable path. * 7. Testing logic circuits 7.1 The need for testing 7.2 Faults and fault models 7.3 Generating test vectors 7.4 Testing sequential circuits 7.1 The need for testing ? How to know a fault exists? By applying test signals to the primary inputs and observe the primary outputs. If the outputs are different from what is expected, we know a fault exists. ? Why is it necessary for testing ? Detect the reasons for faults, and feed the results back to improve the fabrication process. 7.1 The need for testing ? What’s affecting the testing effect? The testing effect depends on the degree to which the internal nodes can be controlled and observed. Often, we do not need to find the specific location of the fault, but only that a fault exists in the device. 7.2 Faults and fault models 1. Fault models In general, faults can be modeled by the effect they have on the functionality of the circuit. Fault models can be divided into two types ? logic fault models, parametric fault models. ? Logic fault models Logic fault models deal with faults that affect the logic function of the circuit. ? Parametric fault models Parametric fault models deal with faults that affect the magnitude of circuit parameters such as voltage, current. 7.2 Faults and fault models 2. Stuck-at fault Many faults can be modeled as causing a permanent logic 1 or a permanent logic 0 on a signal path (input or output of a gate). Stuck-at-1 fault A fault leading to a permanent logic 0 on a signal path is called stuck-at-0 (s-a-0). A fault leading to a permanent logic 1 on a signal path is called stuck-at-1 (s-a-1). ? Stuck-at-0 fault 7.2 Faults and fault models 3. Other types of fault Stuck-on fault The type of internal short or open fault leading