Pipelined ADC Digital Calibration Techniques and Tradeoffs英文文献.pdfVIP

Chapter 2 Pipelined ADC Digital Calibration Techniques and Tradeoffs Imran Ahmed Abstract In this paper an overview of state of the art techniques to measure and correct non-idealities in a pipelined ADC is given. The paper discusses the moti- vations for digital calibration, and subsequently details state of the art calibration approaches. System tradeoffs of commonly used calibration techniques are an- alyzed. A discussion of how digital calibration can be used to enable the next generation of very low power ‘smart-ADCs’ is also given. 2.1 Introduction The pipelined topology is a popular option for ADCs which require resolutions on the order of 8 to 14 b and sampling rates between a few MS/s to hundreds of MS/s. The popularity of the topology can be attributed to its relatively simple and repetitive core structure, as well as a significant reduction in the number of com- parators required to achieve a fixed resolution when compared to other Nyquist-rate data converters such as Flash, folding Cinterpolating, etc. Pipelined ADCs are used in a variety of applications such as: mobile systems, CCD imaging, ultrasonic medi- cal imaging, digital receivers, base stations, digital video (e.g. HDTV), xDSL, cable modems, and fast Ethernet. With the use of pipelined ADCs in many consumer products, research in improving the performance of pipelined ADCs has attracted much attention over the past decade, where the most popular areas of research have been: linearity enhancement, and power reduction. Linearity enhancement has been an active area of research as with deep sub- micron technology low intrinsic gain from MOSFETs, low supply voltages, and device mismatch have made achieving very linear data converters (i.e. 10-b lin- ear) challenging using conventional pipelined ADC design techniques. Low power consumption in pipelined ADCs is motivated by the fact that for mobile sys