数据库 ch7_2m.ppt

?未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn VHDL Simulation Synthesis Agenda Code Block Code Reuse Test Platform Code Block Using Block and Process Clause to Separate Large Code Example of Block Clause library ieee; use ieee.std_logic_1164.all; entity blkblk is port(X: in std_logic; Y: out std_logic); end blkblk; architecture blkblk_arch of blkblk is signal A, B: std_logic; begin u1: block signal C, D: std_logic; begin A = C; B = D;C = X; D = X; end block u1; u2: block signal C, E: std_logic; begin C = A; E = B; u3: block signal E, F, G: std_logic; begin E = A; F = E; G = u2.E; end block u3; end block u2; Y = X and (A or B); end blkblk_arch; Example of Process Clause (1) Example of Process Clause (2) library ieee; use ieee.std_logic_1164.all; ENTITY fsm IS PORT(clock,x : IN BIT; z : OUT BIT); END fsm; ------------------------------------------------- ARCHITECTURE behaviour OF fsm IS TYPE state_type IS (s0, s1, s2, s3); SIGNAL present_state,next_state : state_type; BEGIN --state register process state_reg: PROCESS BEGIN WAIT UNTIL clockEVENT AND clock = 1; present_state = next_state; END PROCESS; Example of Process Clause (3) Agenda Code Block Code Reuse Test Platform Component Port Map 子模块通过接口来描述，便于分工合作。 不同进度的设计模块可以参与系统调试。 结合Configuration可以灵活地测试不同的设计版本的差异。 Component Port Map (Example 1) Component Port Map (Example 2) Port Map … component YYY port (a, b: in bit; c: out bit); end component; ... singal A1, B1, C1: bit; singal A2, B2, C2: bit; ... u0: YYY port map(A1, B1, C1); u1: YYY port map(a=A2, b=B2, c=C2); … Agenda Code Block Code Reuse Test Platform Code Structure (1) Code Structure (2) Test Platform (Example 1) library ieee;use ieee.std_logic_1164.all;entity dff is port( d, clk: in std_logic;