2-Verilog语言基础3.ppt

January 2006 Verilog Digital System Design Copyright Z. Navabi, 2006 1 Verilog 语法的基本概念 电子信息学院 姜小波 2005 Verilog HDL 2 System Tasks (cont’d) reg [4:0] port_id; $display(“ID of the port is %b”, port_id); Output: ID of the port is 00101 reg [3:0] bus; $display(“Bus value is %b”, bus); Output: Bus value is 10xx $display(“Hierarchical name of this module is %m”); Output: Hierarchical name of this module is top.p1 $display(“A \n multiline string with a %% sign.”); Output: A multiline string with a % sign. 2005 Verilog HDL 3 System Tasks (cont’d) $monitor: monitors a sig