2-Verilog语言基础3.ppt

January 2006 Verilog Digital System Design Copyright Z. Navabi, 2006 1 Verilog 语法的基本概念 电子信息学院 姜小波 2005 Verilog HDL 2 System Tasks (cont’d) reg [4:0] port_id; $display(“ID of the port is %b”, port_id); Output: ID of the port is 00101 reg [3:0] bus; $display(“Bus value is %b”, bus); Output: Bus value is 10xx $display(“Hierarchical name of this module is %m”); Output: Hierarchical name of this module is top.p1 $display(“A \n multiline string with a %% sign.”); Output: A multiline string with a % sign. 2005 Verilog HDL 3 System Tasks (cont’d) $monitor: monitors a signal when its value changes Syntax: $monitor(p1, p2, p3, …, pn); p1,…, pn can be quoted string, variable, or signal names Format specifiers just as $display Continuously monitors the values of the specified variables or signals, and displays the entire list whenever any of them changes. $monitor needs to be invoked only once (unlike $display) Only one $monitor (the latest one) can be active at any time $monitoroff to temporarily turn off monitoring $monitoron to turn monitoring on again 2005 Verilog HDL 4 System Tasks (cont’d) $monitor Examples: initial begin $monitor($time, “Value of signals clock=%b, reset=%b”, clock, reset); end Output:0 value of signals clock=0, reset=15 value of signals clock=1, reset=110 value of signals clock=0, reset=0 2005 Verilog HDL 5 System Tasks (cont’d) $stop: stops simulation Simulation enters interactive mode when reaching a $stop system task Most useful for debugging $finish: terminates simulation Examples: initial begin clock=0; reset=1; #100 $stop; #900 $finish; end 2005 Verilog HDL 6 Compiler Directives General syntax: `keyword `define: similar to #define in C, used to define macros `macro_name to use the macro defined by `define Examples: `define WORD_SIZE 32 `define S $stop `define WORD_REG reg [31:0] `WORD_REG a_32_bit_reg; 2005 Verilog HDL 7 Compiler Directives (cont’d) `include: Similar to #include in C, includes entire