基于Verilog的密勒码编译码器设计.docxVIP

实验三 基于Verilog的密勒码编译码器设计程序设计编码器module miller_encoder(signal_in,signal_out,clk,o_start,o_finish );//输入输出端口声明input signal_in;input clk;output reg signal_out;//编码串行输出数据output reg o_start;//编码数据开始输出指示output reg o_finish;//编码数据输出完毕指示//内部变量声明reg [7:0] datain_parallel=0;//待编码数据转并行暂存reg [15:0] outbuf_parallel=0;//编码后输出并行数据暂存reg [3:0] count=0;reg d_finish=0;//数据输入完毕指示reg c_finish=0;//编码完毕指示reg clk2=0;//分频时钟integer i,k=15;//本进程用来串并转换always @ (posedge clk2)//输入用clk的二分频时钟，来保证时间相等begin count=count+1;if(count==9)begincount=8;d_finish=1;//串行数据输入完毕，可以开始计算了endelsebegin datain_parallel={datain_parallel[6:0],signal_in};endend//本进程用来产生2分频always @ (posedge clk)begin clk2=~clk2;end//本进程用来并串转换，因为老师说输入输出都得是串行且时间相等always @ (posedge clk)//输出用clk时钟begin if(c_finish==1)//编码完毕了，可以输出鸟begino_start=1;signal_out=outbuf_parallel[k];k=k-1;if(k0)//数据输出完毕 begino_finish=1;signal_out=0;endendelsebeginsignal_out=0;endendalways @(posedge clk2)beginif(d_finish==1)//当串行数据全输入完毕，才开始计算。begincase(datain_parallel[7:6])2b00:outbuf_parallel[15:12] = 4b0011;2b01:outbuf_parallel[15:12] = 4b0001;2b10:outbuf_parallel[15:12] = 4b0111;2b11:outbuf_parallel[15:12] = 4b0110;default:outbuf_parallel[15:12] = 4b0000;endcasefor(i = 5;i = 0; i = i-1)case(datain_parallel[i])b1:begincase(datain_parallel[i+1])b1:begincase({outbuf_parallel[2*i+3],outbuf_parallel[2*i+2]})2b10:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b01;2b01:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b10;endcaseendb0:begincase({outbuf_parallel[2*i+3],outbuf_parallel[2*i+2]})2b00:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b01;2b11:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b10;endcaseendendcase endb0:begincase(datain_parallel[i+1])b1:begincase({outbuf_parallel[2*i+3],outbuf_parallel[2*i+2]})2b10:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b00;2b01:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b11;endcaseendb0:begincase({outbuf_parallel[2*i+3],outbuf_parallel[2*i+2]})2b00:{outbuf_parallel[2*i+1],outbuf_parallel[2*i]} = 2b11;2b11:{outbu