02 嵌入式系统开发-Chapter2-嵌入式硬件系统基础.ppt

* * * * * * * ARM is designed to efficiently access memory using a single memory access cycle. So word accesses must be on a word address boundary, halfword accesses must be on a halfword address boundary. This includes instruction fetches. Point out that strictly, the bottom bits of the PC simply do not exist within the ARM core - hence they are ‘undefined’. Memory system must ignore these for instruction fetches. * Saved processor status register * The condition code flags in the CPSR can be tested by most instructions to determine whether the instruction is to be executed. The condition code flags are usually modified by: ? Execution of a comparison instruction (CMN, CMP, TEQ or TST). ? Execution of some other arithmetic, logical or move instruction, where the destination register of the instruction is not R15. Most of these instructions have both a flag-preserving and a flag-setting variant, with the latter being selected by adding an S qualifier to the instruction mnemonic. Some of these instructions only have a flag-preserving version. This is noted in the individual instruction descriptions. * * A bit - an imprecise data abort is one which occurs as a result of a data access which is asynchronous to the instruction which caused it e.g. a write which is placed in a write buffer and only accesses external memory some time later. In general imprecise data aborts are not easily recoverable. In any case, they can occur at unexpected and inconvenient times e.g. when already in abort mode dealing with an earlier abort. Setting the A bit masks imprecise aborts so that they will not be taken immediately - a pending abort will be taken when the A bit is cleared. The A bit is automatically set on entry to Abort/FIQ/Reset exceptions. E bit controls endianness of data accesses. Set for big-endian, clear for little-endian. Cleared on reset. Set and cleared by SETEND instruction in ARM/Thumb. Load/Store of words or halfwords are byte-reversed if the E bit is set. G