VHDL程序设计基础4-3.pptVIP

VHDL程序设计基础 组合电路设计 8-3优先编码器 library ieee; use ieee.std_logic_1164.all; entity coder83 is port(din:in std_logic_vector(7 downto 0); coder:out std_logic_vector(2 downto 0)); end coder83; architecture behav of coder83 is begin process(din) begin if(din(7)=0)then coder=000; elsif(din(6)=0)then coder=001; elsif(din(5)=0)then coder=010; elsif(din(4)=0)then coder=011; elsif(din(3)=0)then coder=100; elsif(din(2)=0)then coder=101; elsif(din(1)=0)then coder=110; elsif(din(0)=0)then coder=111; end if; end process; end behav; library ieee; use ieee.std_logic_1164.all; entity cc is port(a,b:in std_logic_vector(3 downto 0); y1,y2,y3:out std_logic); end cc; architecture behav of cc is begin process(a,b) begin if ab then y1=1; y2=0; y3=0; elsif a=b then y1=0; y2=1; y3=0; else y1=0; y2=0; y3=1; end if; end process; 加法器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY adder IS PORT(a, b, cin: IN STD_LOGIC; s, co: OUT STD_LOGIC); END adder; ARCHITECTURE rtl OF adder IS BEGIN PROCESS (a, b, cin) VARIABLE axb ,ab, axbc:STD_LOGIC; BEGIN axb:=a XOR b ; ab:=a AND b; axbc:=axb AND ci ; s=ci XOR axb; co=axbc OR ab; END PROCESS; END rtl; * * LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY adder4 IS PORT(a,b :IN STD_LOGIC_VECTOR(3 DOWNTO 0); cin:IN STD_LOGIC; c3:OUT STD_LOGIC; s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END adder4; ARCHITECTURE rtl OF adder4 IS COMPONENT adder PORT(a,b,cin:IN STD_LOGIC; s,co:OUT STD_LOGIC); END COMPONENT; SIGNAL c0,c1,c2:STD_LOGIC; BEGIN u0:adder PORT MAP(a=a(0),b=b(0),cin=cin,s=s(0),co=c0); u1:adder PORT MAP(a=a(1),b=b(1),cin=c0,s=s(1),co=c1); u2:adder PORT MAP(a(2),b(2),c1,s(2),c2); u3:adder PORT MAP(a(3),b(3),c2,s(3),c3); END rtl; 8位加法器 library ieee; us