Chapter 2 Architecture Overview TI C5000官方教材.ppt

DSP C5000;Objectives;C5000;Common Architectural Features of DSPs;Common Architectural Features of DSPs;DSP Requires Multiply and Accumulate;Multiply and Accumulate Unit;Multiple Buses;Internal Memory for Fast Access;Instruction Pipeline for Fast Execution;Sequential Processing of Instructions;Less Cycles per InstructionLess Power Consumption;Texas InstrumentsC5000 Solutions;Basic Harvard Architecture1st DSP Generation;TMS320C54X DSP Generation Block Diagram;TMS320C54X Key Features;C54X Memory Blocks;TMS320C55X DSP Block Diagram;TMS320C55x Key Features;More C55x Features;Comparison Between C54x and C55x;Performances Features Comparison Between C54x and C55x;Same family but big differences!;Convolution with the C54x 1 of 2;Convolution with the C54x 2 of 2;With the C55x it can be done faster!;XPC;C55x Architecture;C55x Program and Instruction Units;C55x Addressing Unit (AU);C55x Data Computation Unit (DU);C55x Writes (E and F buses);C54x Block Diagram;Focus on C54x Architecture;C54x Block Diagram;C54x Pipeline;C54x Memory and Buses;C54 Pipeline Phases;C54x Pipeline Bus/Hardware Use;Pipeline Implications 1 of 3;Pipeline Implications 2 of 3;;C5409 Memory Maps;C5409 Program Memory Options (Page 0);C5409 8M x 16 Program Space;C5409 Data Memory;C5409 Peripheral Overview;C54x Review;C54x Review - Answers;Focus on C55x Architecture;Functional Diagram of C5510 1 of 2 ; Functional Diagram of C5510 2 of 2;;C55x Fetch Packet Pipeline;D;D Read six bytes from the instruction buffer queue. Decode an instruction pair or a single instruction. Dispatch instructions to the appropriate CPU functional units. Read STx_55 bits associated with data address generation: ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC) AD Read/modify registers involved in data address generation. Perform operations that use the A-unit ALU. Decrement ARx for the conditional branch instruction Evaluate the condition of the XCC instruction AC1 Memory read operations, send addresses on the ap