基于FPGA的I2C实验Verilog源代码.docxVIP

`timescale 1ns / 1psmodule i2c_drive( clk,rst_n, sw1,sw2, scl,sda, dis_data );input clk; // 50MHzinput rst_n; //复位信号，低有效input sw1,sw2; //按键1、2,(1按下执行写入操作，2按下执行读操作)output scl; // 24C02的时钟端口inout sda; // 24C02的数据端口output [7:0] dis_data; //输出指定单元的数据//--------------------------------------------//按键检测reg sw1_r,sw2_r; //键值锁存寄存器，每20ms检测一次键值 reg[19:0] cnt_20ms; //20ms计数寄存器always @ (posedge clk or negedge rst_n) if(!rst_n) cnt_20ms = 20d0; else cnt_20ms = cnt_20ms+1b1; //不断计数always @ (posedge clk or negedge rst_n) if(!rst_n) begin sw1_r = 1b1; //键值寄存器复位，没有键盘按下时键值都为1 sw2_r = 1b1; end else if(cnt_20ms == 20hfffff) begin sw1_r = sw1; //按键1值锁存 sw2_r = sw2; //按键2值锁存 end//---------------------------------------------//分频部分reg[2:0] cnt; // cnt=0:scl上升沿，cnt=1:scl高电平中间，cnt=2:scl下降沿，cnt=3:scl低电平中间reg[8:0] cnt_delay; //500循环计数，产生iic所需要的时钟reg scl_r; //时钟脉冲寄存器always @ (posedge clk or negedge rst_n) if(!rst_n) cnt_delay = 9d0; else if(cnt_delay == 9d499) cnt_delay = 9d0; //计数到10us为scl的周期，即100KHz else cnt_delay = cnt_delay+1b1; //时钟计数always @ (posedge clk or negedge rst_n) begin if(!rst_n) cnt = 3d5; else begin case (cnt_delay) 9d124: cnt = 3d1; //cnt=1:scl高电平中间,用于数据采样 9d249: cnt = 3d2; //cnt=2:scl下降沿 9d374: cnt = 3d3; //cnt=3:scl低电平中间,用于数据变化 9d499: cnt = 3d0; //cnt=0:scl上升沿 default: cnt = 3d5; endcase endend`define SCL_POS (cnt==3d0) //cnt=0:scl上升沿`define SCL_HIG (cnt==3d1) //cnt=1:scl高电平中间,用于数据采样`define SCL_NEG (cnt==3d2) //cnt=2:scl下降沿`define SCL_LOW (cnt==3d3) //cnt=3:scl低电平中间,用于数据变化always @ (posedge clk or negedge rst_n) if(!rst_n) scl_r = 1b0; else if(cnt==3d0) scl_r = 1b1; //scl信号上升沿 else if(cnt==3d2) scl_r = 1b0; //scl信号下降沿assign scl = scl_r; //产生iic所需要的时钟//---------------------------------------------//需要写入24C02的地址和数据 `define DEVICE_READ 8b1010_0001 //被寻址器件地址（读操作）`define DEVICE_WRITE 8b1010_0000 //被寻址器件地址（写操作）`define WRITE_DATA 8b0000_0111 //写入EEPROM的数据`define BYTE_ADDR