剩余类数对ira-ldpc码编解码器设计-design of codec for ira - ldpc code with residual class number.docxVIP

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剩余类数对ira-ldpc码编解码器设计-design of codec for ira - ldpc code with residual class number.docx

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剩余类数对ira-ldpc码编解码器设计-design of codec for ira - ldpc code with residual class number

华华中科技大学硕士学位论文 II II Abstract Low-density parity check (LDPC) codes is the best error correcting code which approaches Shannon‘s capacity limit. LDPC code has good asymptotic performance, with decoding complexity linearly proportional to the codes length. This paper supported by National Natural Science Foundation of China ―The Research of Key Technology in Noncoherent MIMO Communication System‖, studies design of encoder and decoder of IRA-LDPC codes based on residue class pairs showed in [50]. BP algorithm, Min-Sum algorithms and two modified Min-Sum algorithms have been studied. Simulation results show that the performance of modified Min-Sum which has only addition and comparison operations can reach 0.1dB as close as about to BP. So Min-Sum algorithms have the good balance between the complexity and performance. On the basis of Check matrix of IRA-LDPC codes, a low hardware complexity encoder structure is designed. The encoder design greatly reduces the storage of the parity check matrix and has the advantages of low coding delay. Finally, the decoder which is based on Offset-Min-Sum algorithm is designed for IRA-LDPC codes with. On the implementation of Offset Min-Sum algorithm, decoder design greatly reduces the storage of the intermediate variables and optimize the storage unit.The decoder has a degree of parallelism L. Based on the cycle characteristics of check matrix of IRA-LDPC codes, the paper designs a suitable storage architecture which is very conducive to the implementation of shuffle network and RAMS memory addressing. The implementation of the variable node calculation unit and a check node calculation unit is regardless of the type of LDPC codes. Simulation showed that the 6-bit quantization for Nodes information can achieve a good compromise between performance and complexity. Key words: IRA-LDPC codes Residue class pairs Encoder Decoder Min-Sum-algorithm Offset- Min-Sum-algorithm PAGE IV PAGE IV 目录摘要 ··························