基于SJTAG的系统级测试研究-测试计量技术及仪器专业论文.docxVIP

摘要 摘 要 随着边界扫描测试技术的不断深入研发，它已经突破了传统管脚接触式测试理论 和手段，解决了传统技术所不能完成的大规模集成电路的检测?虽然边界扫描技术针 对不同的测试类型和测试任务，形成了一系列的国际标准，但在系统级测试方向，仍 然缺乏一个行之有效的通用的国际标准? 本文针对目前系统级测试的实现方案进行了深入研究，并结合 SJTAG（System Joint Test Action Group）工作组提出的系统级测试建议，从硬软两方面改进了系统级 测试?一方面搭建了以 1149.1 协议为基础，JTAG 总线为架构的系统级测试系统硬件 环境?该测试系统以主从方式链接，由一块主控板和多个测试单板组成?主控板发出 JTAG 测试总线，各个测试单板都与测试总线并行链接?主控板控制测试单板的选通 与断开，也同时控制测试单板上边界扫描测试?另一方面，在已有测试平台条件下， 对已有的软件的测试程序??测试算法做了部分改善，使其可以更适应系统级测试要 求，较好的完成系统级测试任务? 本文采用硬件描述语言 VerilogHDL，在 Quartus II 仿真软件平台上，对本文设计 的系统级测试系统的各个模块，分别进行功能设计和仿真验证?通过对仿真波形的具 体分析，结果表明本文的系统级测试系统达到了预期的设计要求?本文的研究工作对 于边界扫描技术在系统级测试方面的应用，有着重要的意义，同时本测试系统实现方 便，具备良好的通用性，应用前景较好? 关键词：SJTAG；IEEE1149.1 标准；JTAG 总线；SJTAG 软件 Abstract Abstract With the deepening of research and development of the boundary-scan testing techniques, it has broken through the traditional pin-contact test theory and means， to solve the traditional technologies which can not be completed VLSI testing. Although the boundary-scan technology for different types of testing and testing tasks has formed a series of international standards, but at the system level test direction, there is still lack of an effective common international standards. The paper, during the current system-level test program conducted in-depth study, combined SJTAG Working Group on the system level testing recommendations, improve system-level tests from hardware and software.On the one hand, it builded system-level test system hardware environment, based on the 1149.1 protocol and JTAG bus architecture. The link mode of the test system is based on mode of Master-Slave，there is a main control board and a lot of test single board in the system. The control board can send out the JTAG test bus, and each test board join in the system by parallel with the test bus link. The control board can control each test board gating and disconnect, at the same time it can control the boundary scan test of the sting single-board. On the other hand, under the conditions of existing test platform