基于SpyGlass的同步设计分析与静态验证-软件工程专业论文.docxVIP

摘 要 随着数字系统复杂度的提高，系统芯片中集成的模块数量增加。各模块通常 工作在不同的时钟频率下，对各系统之间的数据 CDC（Clock Domain Crossing） 通信需要进行同步设计。对于不同时钟域和电压域的情况，对 CDC 同步设计的 要求不同。对于这些 CDC 传输路径以及同步设计的检查验证，在整个设计流程 中的作用日渐凸显。目前还没有一套比较成熟、完善的验证手段，能在设计早期 RTL 级就能完成 CDC 的验证工作。本论文通过分析 CDC 传输中的亚稳态机理， 总结了各种同步设计的优劣以及传统验证方法在 CDC 检查中的弊端，提出并搭 建了一套基于 SpyGlass 的 CDC 静态验证流程。在 RTL 级脱离验证平台和测试向 量，穷举设计中所有 CDC 传输路径并进行了验证。基于不同的验证结果，对设 计缺陷提出了建议性修改方案。经过实际项目的检验，证实该验证手段在设计流 程中是可行有效的，对 CDC 设计与验证有一定借鉴意义。 关键字：数字集成电路 亚稳态 平均失效时间 同步设计 静态验证 Abstract So many module blocks are integrated in current digital SOC with the increasing of the complexity. Such modules are all working under different clock frequencies commonly. Clock domain crossing of the data among modules always need to be synchronized by dedicated designs. There are different requirement in the sync designs, with regard to the different clock-domain or power-domain scheduling. So the verifications for such clock domain crossing paths and inserted data sync cells become more and more important in IC design flow. Currently there is stilling not perfect method to solving this issue in early designing stage. All diff sync designs‘ merits and the traditional verification methods‘ weakness upon CDC aspect in current flow are made a conclusion based on analyzing of the CDC meta-stability mechanism in this thesis. Meanwhile, a static verification environment and flow based on SpyGlass tool without test bench and test case in RTL level are introduced and built. Based on this new verification method all the CDC paths in design are exhausted and carried on examinations. Some changing suggestions for the common RTL design defects are given as well in the article. It is shown that this static verification method is feasible by application in IC project, which are reference meaning to the CDC design and verification part. Keyword: Digital-IC Meta-stability MTBF（Mean Time Between Failures） Synchronization design Static verification 目录 HYPERLINK \l _bookmark0 第一章 绪 论 1