StratixV高速差分IO接口和DPA.PDFVIP

Stratix V高速差分I/O接口和DPA 6 2014.01.10 SV51007 订阅 反馈 Stratix V器件中的高速差分I/O接口和动态相位对齐器(DPA)功能对单端I/O提供优势，并在实现总 体系统带宽中发挥了作用。Stratix V器件支持低电压差分信号(LVDS)、mini-LVDS和RSDS差分I/O 标准。 下图显示了Stratix V器件中高速差分I/O支持的I/O bank 。 图6-1: 高速差分I/O支持的I/O Bank LVDS I/Os I/Os with Dedicated SERDES Circuitry LVDS Interface LVDS Interface with Use External PLL with Use External PLL Option Enabled Option Disabled 相关链接 • Stratix V器件手册: 已知问题 列出了对Stratix V器件手册章节所规划的更新。 • Stratix V器件中的I/O特性 提供了关于所支持的差分I/O标准的信息。 Stratix V器件中的专用高速电路 下面的专用电路可用于Stratix V器件系列来支持高速差分I/O ： • 差分I/O 缓冲器 • 发送串化器 • 接收解串器 • 数据重对齐模块(Bit-slip) © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Alteras standard warranty, but reserves the right to make changes to any products and services at