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- 约7.14万字
- 约 62页
- 2018-12-28 发布于广东
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Abstract
Abstract
the
WheIl ofVLSI leVel
dcVelopm肌t tecllllologyst印intode印一submicron
ofintercollIlecte虢ctinVLSIbecomemore mall
(DSM),the
impact inlportant
before.IntercolⅡleCt AnteIⅡla
delay,CrosstalkE虢ct,IR—Drop,EME虢Ct,Process
E虢cthaVebecomethebottle-neckofthe new
physicaldesi髓andbringschallenge.
FiVeinterconnecte毹ctmelltionedaboVeare detailedintllis
a11alyzed p印er.
Methodto and
fixintercoImecte腩ctisusedinⅥ~KSoC
prevent chip’sdesi伊,
thecontinuous andmanufactur
ensuring under driven.
coIⅣergence a_bility timing
v矗ficationYAK are
Lo西cs叫hesis,physical of SOC in
desi盟and presented
mis suChas
p印既Someimport锄processn00叩laIlning,IOplac锄ent,clock
are YAKSOCis
syllmesis,routingaIlalyzed.Tllephysicaldesi印of completed
Success龟1.TheGDSII filecould如lfillwiththe
layout timingrequirement锄d
me DRCand
LVSv嘶6cationhave
implementanticipatiVe劬ction.Since process
isableto out.
6nished,mis
layout t印e
YAKSOCisaSoC ourlab.Itsareais use
chipdesi印edby 3200叫l×3300pm.n
HJTc’s180m andis
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