三维叠层芯片封装的可靠性分析.pdfVIP

ABSTRACT ABSTRACT With the development of electronic technology, three-dimensional packaging is developed to meet the requirements of smaller size and higher densit package. Stacked die package is a widel used three-dimensional packaging technology, it improves the densit of electronic products, reduces the interconnect wire length between the chips, increases the operating speed of the device and achieved multifunction in a device. But the rapid increase in integration densit electronic packaging is bound to higher requirement of thermal conductivity, dielectric properties, performance of packaging materials. So, it requires development of new packaging materials and technologies. At the same time, electronic components are hosted b higher mechanical, thermal, electrical stress, so the stud on reliabilit of stacked die package is more and more important. Stacked die package needs to multiple chips vertically, the adhesive between chips, chips and lead frame, chips and the plastic material and interconnection is the key. In this paper, the wa to achieve interconnection is wire bonding. In order to avoid major changes to the packaging process, reduce the thickness of the stacked die to ensure that the overall package thickness unchanged. However, reducing the thickness of the chips will cause the chip to reduce the stiffness. Deformation easil occur during heat treatment, it ma cause die chipping and crack. Further, due to the reduced thickness of the plastic, the abilit to prevent moisture intrusion in interface of material will be reduced and will lead to delamination and cracks. This paper design parameters for the experiment based on these conclus