FPGA布局算法的-研究与实现.doc

哈尔滨工业大学工学硕士学位论文 Abstract With the rapid development of Electronic Technology, the application of integrated circuit is on a large scale, the FPGA（Field-Programmable Gate Array）has been widely used as Field Programmable Gate Array devices. At the same time, also require a small design cycle of the FPGA, so it is possible to keep up with the progress of science and technol HYPERLINK javascript:void(0); ogy. HYPERLINK javascript:void(0); HYPERLINK javascript:void(0); Placement HYPERLINK javascript:void(0); HYPERLINK javascript:void(0); is HYPERLINK javascript:void(0); HYPERLINK javascript:void(0); an HYPERLINK javascript:void(0); HYPERLINK javascript:void(0); important step during design procedure of FPGA, which is HYPERLINK javascript:void(0); a HYPERLINK javascript:void(0); HYPERLINK javascript:void(0); connecting HYPERLINK javascript:void(0); HYPERLINK javascript:void(0); link HYPERLINK javascript:void(0); between process Mapping and Routing, and has an important influence on wire-length, the CPU run time, Timing and so on. This article research and implement the algorithm for FPGA, realizing three algorithms based on research analysis. FARPLACE layout algorithm adopts the quadratic wire-length and disturbed nodes to complete the layout, adding disturbed nodes to movable units inside of the chip, making movable units which in chip to new locations by the external force and achieve layout. After researching wire-length model and the density model and then design all of them. When the design is complex, the result on performance of above algorithm is not so good. Therefore, on the basis of FARPLACE algorithm completed, we research and design multi-level layout algorithm based on FARPLACE. Multi-level algorithm is based on the connection strength between the unit and unit, all packaged units as a unit for layout, iterative FARPLACE process can obtain better results. The above two algorithms of wire-length and density is optimized step by