多元ldpc码编译码器的设计与实现通信与信息系统专业论文.docxVIP

AbstractAbstract Abstract Abstract Recently，low-density parity—check(LDPC)codes have attracted much attention because of their excellent error-correcting performence and highly parallelizable decoding scheme，they will be considered as error—correcting codes for next generation communication systems．LDPC codes over GF(q)are all extension of binary LDPC codes that have not been studied extensively．However，performance of GF(q) LDPC codes have been shown tO be higher than binary LDPC codes，and they have great potential of their application prospects． The highly hardware complexity and area of the decoder are the important reason for restricting their development．In this paper,putting the code and decoder design together to consider,we propose a FPGA implementation based on the quasi—cyclic RA coding algorithm，extended min—sum(EMS)decoding algorithm for LDPC codes over GF(q)．Function，structure，working principle and design details are systemically discussed．Quasi—cyclic codes can facilitate efficient high—speed parallel decoding．RA structure largely reduces the coding complexity,and the EMS algorithm greatly simplifies the decoding complexity and resource consumption．Based on this architectures the LDPC codes over GF(4)decoder is implemented on Xilinx field programmable gate array(FPGA)．The result shows the maximum encoding clock 丘equency is 1 23．277MHz，and the throuthput is 246．554Mbiffs，the maximum decocoding clock frequency is 175．352MHz and the throughput is 87．676MbitS／s．Some correlation analysis and comparisons prove its availability．This paper presents scheduling algorithm effectively improving the utilization of the clock and throughput． about 1．93 times more than before． According to these，the main research contents include： First，a brief introduction about construction methods of LDPC codes and several COITllTlOn decoding algorithms has been done．The structure of RA construction methods and EMS decoding algorithm in details are described． Second,seve