基于CMOS工艺的10位逐次逼近型模数转换器设计-微电子学与固体电子学专业论文.docxVIP

摘要摘要 摘要 摘要 随着现代通信系统、便携式消费电子和汽车电子等应用领域的不断发展，促 使高性能、低功耗、低成本的SOC成为当今集成电路设计的主要趋势。SOC的发 展要求ADC、其它模拟电路与DSP集成在一个芯片上，本论文的目的是设计一款 中等精度、低功耗、小尺寸的ADC来满足SOC的发展需求。 本文基于CMOS工艺对10位精度逐次逼近型ADC的主要功能模块进行了设 计。在预放大锁存比较器设计中采用失调自校准技术，消除了失调电压，采用 Cadence软件对比较器电路进行了仿真，结果表明，比较器增益达到85dB，分辨 能力达0．28mV，功耗为0．14roW，满足高速、高精度、低功耗的性能要求。采用 高6位的二进制权重电容阵列和低4位的电阻阵列的组合结构，设计了一种改进 的电荷重分配型DAC，降低了电容匹配性要求，减小了非线性误差。通过对DAC 的仿真分析表明该电路具有速度快、线性好的特点。讨论了电容和电阻的失配对 DAC非线性的影响，给出了提高DAC性能的设计原则。基于混合信号集成电路 版图设计的考虑，完成了逐次逼近型ADC核心电路的版图设计，版图面积为 957¨m×849衄1。 关键词：逐次逼近模数转换器 比较器失调电压 AbstractWith Abstract With the continuous development of application field for wireless communication， portable consumer electronics and automotive electronics，hi曲一performance， low-power,low·cost SOC become main trend of integrated circuit design．The development of SOC re．quires A／D converter,other analog circuits and DSP to be integrated in a chip．The purpose of this thesis is to design a medium—solution, low-power,small—size SAR A／D converter to meet the development needs of SOC． In this thesis，module circuits design of a l O-bit resolution，low-power,small—size SAR A／D converter based on CMOS technology is presented．To cancel offset voltage，a preamplifier-latch comparator using self-calibration technique is adopted．Simulated by Cadence，the comparator Can achieve 85一dB gain,0．28-mV sensitivity and 0．14-mV power consumption．All the simulation results meet the performance requirement of high-speed,high—solution and low-power．Design a modified charge-redistribution DAC by combining 6-bit MSBs’binary wei班ted capacitor array and 4-bit LSBs’resistor array．The DAC can lower nonlinear eITor and the requirement of capacitors’matching． Simulation reveals the DAC achieves high speed and linearity．Influence of DAC’S nonlinearity due to capacitor and resistor’S mism．atch is discussed．Principles on how to improve the performance of DAC is also considered．Finally,based on consideration of mix signal IC layout design,the layout of ADC is given．The core area is 957pm